LPC546xx
LPC546xx
On-chip memory:
Up to 512 KB on-chip flash program memory with flash accelerator and 256 byte
Up to 200 KB total SRAM consisting of 160 KB contiguous main SRAM and an
additional 32 KB SRAM on the I&D buses. 8 KB of SRAM bank intended for USB
16 KB of EEPROM.
Flash In-Application Programming (IAP) and In-System Programming (ISP).
ROM-based USB drivers (HID, CDC, MSC, and DFU). Flash updates via USB.
Booting from valid user code in flash, USART, SPI, and I2C.
OTP API for programming OTP memory.
Serial interfaces:
Flexcomm Interface contains up to ten serial peripherals. Each Flexcomm Interface
can be selected by software to be a USART, SPI, or I2C interface. Two Flexcomm
Interfaces also include an I2S interface. Each Flexcomm Interface includes a FIFO
that supports USART, SPI, and I2S if supported by that Flexcomm Interface. A
variety of clocking options are available to each Flexcomm Interface and include a
I2C-bus interfaces support Fast-mode and Fast-mode Plus with data rates of up to
1Mbit/s and with multiple address recognition and monitor mode. Two sets of true
I2C pads also support High Speed Mode (3.4 Mbit/s) as a slave.
Two ISO 7816 Smart Card Interfaces with DMA support.
USB 2.0 high-speed host/device controller with on-chip high-speed PHY.
USB 2.0 full-speed host/device controller with on-chip PHY and dedicated DMA
controller supporting crystal-less operation in device mode using software library.
SPIFI with XIP feature uses up to four data lines to access off-chip SPI/DSPI/QSPI
flash memory at a much higher rate than standard SPI or SSP interfaces.
Ethernet MAC with MII/RMII interface with Audio Video Bridging (AVB) support and
Two CAN FD modules with dedicated DMA controller.
DMA controller with 30 channels and up to 24 programmable triggers, able to
LCD Controller supporting both Super-Twisted Nematic (STN) and Thin-Film
Transistor (TFT) displays. It has a dedicated DMA controller, selectable display
resolution (up to 1024 x 768 pixels), and supports up to 24-bit true-color mode.
External Memory Controller (EMC) provides support for asynchronous static
memory devices such as RAM, ROM and flash, in addition to dynamic memories
such as single data rate SDRAM with an SDRAM clock of up to 100 MHz. EMC bus
width (bit) on TFBGA180, TFBGA100, and LQFP100 and packages supports up to
8/16 data line wide static memory, in addition to dynamic memories, such as,
SDRAM (2 banks only) with an SDRAM clock of up to 100 MHz.
Secured digital input/output (SD/MMC and SDIO) card interface with DMA support.
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